Dynamic circuits are known for their speed advantages over static circuits. Dynamic circuits have application in such areas as microprocessor and memory design, as well as in many other areas.
An example of a typical dynamic circuit is shown in FIG. 1 (a CMOS technology example). When `clock` = `0`, transistor P10 conducts and transistor N10 does not conduct. This precharges the dynamic node `store` to `1`. Node `output` is driven to `0` by static inverter I10, which comprises transistors P14 and N14. When `clock` = `1`, transistor P10 does not conduct and transistor N10 conducts. If the values of `input1` ... `inputN` are such that there exists no conducting path from node `store` to transistor N10, then node `store` remains at `1` and node `output` remains at `0`. If the values of `input1` ... `inputN` are such that there exists a conducting path through transistors N11, N12, N13 ... from node `store` to transistor N10, then node `store` is discharged to `0`, and node `output` is driven to ` 1` by static inverter I10. Transistors N11, N12 ... N13, therefore, implement a desired boolean function that determines under what condition node `output` evaluates to `1`.
FIG. 2 shows a level sensitive latch that can be used with dynamic circuits (a CMOS technology example). When `clock` is `0`, node `clock.sub.-- not` is driven to `1` by inverter I20. Transistors P21 and N21 don't conduct, while transistors P20 and N20 conduct. Inverters I21 and I22 form a latch. When `clock` is `1`, node `clock.sub.-- not` is driven to `0` by inverter I20. Transistors P20 and N20 don't conduct, while transistors P21 and N21 conduct. Inverters I21 and I22 transfer the value at node `input` to node `output`.
The most common way to build a digital system out of dynamic circuits is to use a two-clock clocking scheme, as shown in FIGS. 3 (a) and (b). LOG1s (31 ... 32) are dynamic logic gates controlled by signal `clock1` in FIG. 3 (b). LOG2s (34 ... 35) are dynamic logic gates controlled by signal `clock2`. LAT1 (33) is a latch controlled by signal `clock1`. LAT2s (30 and 36) are latches controlled by signal `clock2`.
When `clock1` = `1` and `clock2` = `0` LOG1s evaluate and their value is written into LAT1s. At the same time, LOG2s precharge and LAT2s hold their data. When `clock1` = `0` and `clock2` = `1` LOG1s precharge and LAT1s hold their data; LOG2s evaluate and their value is written into LAT2s.
When `clock1` = `0` and `clock2` = `0` no logic is performed by either LOG1 or LOG2. This time is called `dead time` and is to be avoided. When `clock1` = `1` and `clock2` = `1` a condition exists where data from LAT2 30 can propagate through LAT1 33 (via LOG1s) into LAT2 36 (via LOG2s) disturbing uniform data flow. This is called `race` and is to be avoided.
There are several shortcomings in the two-clock clocking scheme described above. The goal of any design is to maximize the fraction of cycle time during which logic is being performed. In a typical system, the architectured registers can be represented by LAT2s, and the architectured combinational logic split between LOG1s and LOG2s. FIG. 4 shows that time intervals 40 (LAT2 drive time) and 43 (LAT2 setup time) are not available for performing architectured combinational logic because these times are required by the architectured registers LAT2s. Time intervals 41 (LOG1 evaluate time) and 42 (LOG2 evaluate time) are available for performing architectured combinational logic. However, several factors reduce time intervals 41 and 42.
It is necessary to insert LAT1s between LOG1s and LOG2s to hold data when `clock1` = `0` and `clock2` = `1`, as previously described in FIGS. 3 (a) and (b). When `clock1` = `0`, LOG1s precharge and their outputs go to precharge condition. Thus, LAT1s are required to hold these values for LOG2s.
FIG. 5 shows that time interval 54 is LAT1 setup time and time interval 55 is LAT1 drive time. Time interval 54 reduces time interval 41, leaving time interval 51 for LOG1 evaluation, and time interval 55 reduces time interval 42, leaving time interval 52 for LOG2 evaluation. As a result, less time is available to perform architectured combinational logic.
Typical clocks cannot maintain uniform phase duration without clock jitter. FIG. 6 shows that mid cycle clock jitter 66 further reduces combinational logic time intervals 41 and 42 to time intervals 61 and 62, respectively.
Finally, each dynamic circuit of FIG. 3 (LOG1) has a discrete propagation delay. FIG. 7 shows that it is often not possible to use up the entire time interval 61 with LOG1s of propagation delay 78. As a result, time interval 77 is wasted, since it is not long enough to accommodate another LOG1 delay, leaving only time interval 71. FIG. 7, therefore, illustrates the shortcomings of a two-clock clocking scheme. Time intervals 54, 55, 66, and 77 all reduce time intervals 41 and 42 during which architectured combinational logic is performed.
The invention described below is a novel technique that eliminates undesirable time intervals 54, 55, 66 and 77.